talos

a fast SystemVerilog simulator

counter.sv
A counter with zero-delay scheduling, an assertion, and a strobe The clock toggles every 5 ns. On a positive edge, count is updated by a nonblocking assignment. A zero delay schedules a continuation through Inactive, which resumes in Active and sets seen. An always_comb process updates even after NBA commits count. A concurrent assertion samples count and even in Preponed, evaluates in Observed, and prints its pass action in Reactive. The strobe prints the final count in Postponed. module counter; timeunit 1ns; timeprecision 1ps; bit clk = 0, seen = 0; logic [3:0] count = 0; logic even; always #5 clk = ~clk; always @(posedge clk) begin count <= count + 1; #0 seen = clk; $strobe("count=%0d", count); end always_comb even = ~count[0]; assert property (@(posedge clk) even == ~count[0]) $display("ok"); endmodule
EVENT SCHEDULER
A compact visualization of SystemVerilog event scheduling An original visualization of the scheduling rules in IEEE 1800 section 4.4. Seven exercised regions are shown. Ellipses omit PLI callbacks and unused reactive regions, with their names in tooltips. Across four clock cycles, count advances from zero to four and even alternates. At 5 ns, Preponed samples count as zero and even as one. Active raises the clock and queues count in NBA. A zero delay places the continuation in Inactive; it resumes in Active and sets seen. NBA commits count as one, and Active recomputes even. Observed checks the sampled even/count invariant, Reactive prints ok, and Postponed prints count equals one. Highlighted outgoing and incoming arrows mark advancement to 10 ns, where the clock falls. The same sequence repeats at 15, 25, and 35 ns; the illustrative trace resets after 40 ns. SIMULATION TIME 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns 40 ns previoustime slotnexttime slot previoustime slot nexttime slot Preponed Active Inactive NBA Observed Reactive Postponed Omitted: Pre-Active··· Omitted: Pre-NBA··· Omitted: Post-NBA, Pre-Observed··· Omitted: Post-Observed··· Omitted: Re-Inactive, Pre-Re-NBA, Re-NBA, Post-Re-NBA, Pre-Postponed··· sample 0, 1 sample 1, 0 sample 2, 1 sample 3, 0 sample 1, 0 sample 2, 1 sample 3, 0 sample 4, 1 clk = 1 0 + 1 → 1 1 + 1 → 2 2 + 1 → 3 3 + 1 → 4 #0 suspend #0 continuation seen = 1 queue $strobe count <= 1 count <= 2 count <= 3 count <= 4 count 0 → 1 count 1 → 2 count 2 → 3 count 3 → 4 even = 0 even = 1 even = 0 even = 1 sampled 1 == ~0 sampled 0 == ~1 sampled 1 == ~0 sampled 0 == ~1 $display("ok") "count=1" "count=2" "count=3" "count=4" clk = 0 SIGNALS clk 0 1 count 4'h0 4'h1 4'h2 4'h3 4'h4 seen 0 1 even 1 0
Four clock cycles from 0 to 40 ns through Preponed, Active, Inactive, NBA, Observed, Reactive, and Postponed, followed by a time-slot transition. PLI callbacks and unused reactive regions are collapsed.